Tendrá lugar este jueves 5 de mayo, de 10:00 a 11:00 en el Aula A.05 del Edif. Ada Byron.
SUMMARY: In this talk I will introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated RTL source code of the MIPS microAptiv UP processor. The core is made available by Imagination Technologies for academic use and is targeted to an FPGA, making it ideal for both the classroom and research. The supporting materials and labs focus on hands-on learning that emphasizes computer architecure, System on Chip (SoC) design and hardware-software codesign. Among other things, students learn to set up the MIPS soft-core processor on a field-programmable gate array (FPGA), run and debug programs on the core in simulation and in hardware, add new peripherals to the system, understand the microarchitecture and extend it to support new features, experiment with different cache sizes and content management policies, add new instructions using the CorExtend interface available in MIPS processors, and understand SoCs in embedded systems and how they are designed and built up in layers to run complex software such as Linux.
SHORT BIO: Daniel Chaver received the degree in physics from the University of Santiago de Compostela, Spain, in 1998, and the Electrical Engineering degree and Ph.D. from the Complutense University of Madrid, Spain, in 2000 and 2006, where he is currently an Associate Professor. He has taught many courses related to Computer Science and Electrical Engineering since 2000. He has co-advised 3 PhD thesis and has co-authored more than 40 papers. Since 2015 he collaborates with Imagination Technologies. His current research interests include: (1) architectural techniques for managing efficiently the memory hierarchy and (2) OS scheduling techniques for asymmetric multiprocessors.
